gcc (page 8)

       M32R/D Options

       These -m options are defined for Renesas M32R/D architectures:

       -m32r2
           Generate code for the M32R/2.

       -m32rx
           Generate code for the M32R/X.

       -m32r
           Generate code for the M32R.  This is the default.

       -mmodel=small
           Assume all objects live in the lower 16MB of memory (so that their
           addresses can be loaded with the "ld24" instruction), and assume
           all subroutines are reachable with the "bl" instruction.  This is
           the default.

           The addressability of a particular object can be set with the
           "model" attribute.

       -mmodel=medium
           Assume objects may be anywhere in the 32-bit address space (the
           compiler will generate "seth/add3" instructions to load their
           addresses), and assume all subroutines are reachable with the "bl"
           instruction.

       -mmodel=large
           Assume objects may be anywhere in the 32-bit address space (the
           compiler will generate "seth/add3" instructions to load their
           addresses), and assume subroutines may not be reachable with the
           "bl" instruction (the compiler will generate the much slower
           "seth/add3/jl" instruction sequence).

       -msdata=none
           Disable use of the small data area.  Variables will be put into one
           of .data, bss, or .rodata (unless the "section" attribute has been
           specified).  This is the default.

           The small data area consists of sections .sdata and .sbss.  Objects
           may be explicitly put in the small data area with the "section"
           attribute using one of these sections.

       -msdata=sdata
           Put small global and static data in the small data area, but do not
           generate special code to reference them.

       -msdata=use
           Put small global and static data in the small data area, and
           generate special instructions to reference them.

       -G num
           Put global and static objects less than or equal to num bytes into
           the small data or bss sections instead of the normal data or bss
           sections.  The default value of num is 8.  The -msdata option must
           be set to one of sdata or use for this option to have any effect.

           All modules should be compiled with the same -G num value.
           Compiling with different values of num may or may not work; if it
           doesn't the linker will give an error message---incorrect code will
           not be generated.

       -mdebug
           Makes the M32R specific code in the compiler display some
           statistics that might help in debugging programs.

       -malign-loops
           Align all loops to a 32-byte boundary.

       -mno-align-loops
           Do not enforce a 32-byte alignment for loops.  This is the default.

       -missue-rate=number
           Issue number instructions per cycle.  number can only be 1 or 2.

       -mbranch-cost=number
           number can only be 1 or 2.  If it is 1 then branches will be
           preferred over conditional code, if it is 2, then the opposite will
           apply.

       -mflush-trap=number
           Specifies the trap number to use to flush the cache.  The default
           is 12.  Valid numbers are between 0 and 15 inclusive.

       -mno-flush-trap
           Specifies that the cache cannot be flushed by using a trap.

       -mflush-func=name
           Specifies the name of the operating system function to call to
           flush the cache.  The default is _flush_cache, but a function call
           will only be used if a trap is not available.

       -mno-flush-func
           Indicates that there is no OS function for flushing the cache.

       M680x0 Options

       These are the -m options defined for M680x0 and ColdFire processors.
       The default settings depend on which architecture was selected when the
       compiler was configured; the defaults for the most common choices are
       given below.

       -march=arch
           Generate code for a specific M680x0 or ColdFire instruction set
           architecture.  Permissible values of arch for M680x0 architectures
           are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32.  ColdFire
           architectures are selected according to Freescale's ISA
           classification and the permissible values are: isaa, isaaplus, isab
           and isac.

           gcc defines a macro __mcfarch__ whenever it is generating code for
           a ColdFire target.  The arch in this macro is one of the -march
           arguments given above.

           When used together, -march and -mtune select code that runs on a
           family of similar processors but that is optimized for a particular
           microarchitecture.

       -mcpu=cpu
           Generate code for a specific M680x0 or ColdFire processor.  The
           M680x0 cpus are: 68000, 68010, 68020, 68030, 68040, 68060, 68302,
           68332 and cpu32.  The ColdFire cpus are given by the table below,
           which also classifies the CPUs into families:

           Family : -mcpu arguments
           51qe : 51qe
           5206 : 5202 5204 5206
           5206e : 5206e
           5208 : 5207 5208
           5211a : 5210a 5211a
           5213 : 5211 5212 5213
           5216 : 5214 5216
           52235 : 52230 52231 52232 52233 52234 52235
           5225 : 5224 5225
           5235 : 5232 5233 5234 5235 523x
           5249 : 5249
           5250 : 5250
           5271 : 5270 5271
           5272 : 5272
           5275 : 5274 5275
           5282 : 5280 5281 5282 528x
           5307 : 5307
           5329 : 5327 5328 5329 532x
           5373 : 5372 5373 537x
           5407 : 5407
           5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484
           5485

           -mcpu=cpu overrides -march=arch if arch is compatible with cpu.
           Other combinations of -mcpu and -march are rejected.

           gcc defines the macro __mcf_cpu_cpu when ColdFire target cpu is
           selected.  It also defines __mcf_family_family, where the value of
           family is given by the table above.

       -mtune=tune
           Tune the code for a particular microarchitecture, within the
           constraints set by -march and -mcpu.  The M680x0 microarchitectures
           are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32.  The
           ColdFire microarchitectures are: cfv1, cfv2, cfv3, cfv4 and cfv4e.

           You can also use -mtune=68020-40 for code that needs to run
           relatively well on 68020, 68030 and 68040 targets.  -mtune=68020-60
           is similar but includes 68060 targets as well.  These two options
           select the same tuning decisions as -m68020-40 and -m68020-60
           respectively.

           gcc defines the macros __mcarch and __mcarch__ when tuning for
           680x0 architecture arch.  It also defines mcarch unless either
           -ansi or a non-GNU -std option is used.  If gcc is tuning for a
           range of architectures, as selected by -mtune=68020-40 or
           -mtune=68020-60, it defines the macros for every architecture in
           the range.

           gcc also defines the macro __muarch__ when tuning for ColdFire
           microarchitecture uarch, where uarch is one of the arguments given
           above.

       -m68000
       -mc68000
           Generate output for a 68000.  This is the default when the compiler
           is configured for 68000-based systems.  It is equivalent to
           -march=68000.

           Use this option for microcontrollers with a 68000 or EC000 core,
           including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.

       -m68010
           Generate output for a 68010.  This is the default when the compiler
           is configured for 68010-based systems.  It is equivalent to
           -march=68010.

       -m68020
       -mc68020
           Generate output for a 68020.  This is the default when the compiler
           is configured for 68020-based systems.  It is equivalent to
           -march=68020.

       -m68030
           Generate output for a 68030.  This is the default when the compiler
           is configured for 68030-based systems.  It is equivalent to
           -march=68030.

       -m68040
           Generate output for a 68040.  This is the default when the compiler
           is configured for 68040-based systems.  It is equivalent to
           -march=68040.

           This option inhibits the use of 68881/68882 instructions that have
           to be emulated by software on the 68040.  Use this option if your
           68040 does not have code to emulate those instructions.

       -m68060
           Generate output for a 68060.  This is the default when the compiler
           is configured for 68060-based systems.  It is equivalent to
           -march=68060.

           This option inhibits the use of 68020 and 68881/68882 instructions
           that have to be emulated by software on the 68060.  Use this option
           if your 68060 does not have code to emulate those instructions.

       -mcpu32
           Generate output for a CPU32.  This is the default when the compiler
           is configured for CPU32-based systems.  It is equivalent to
           -march=cpu32.

           Use this option for microcontrollers with a CPU32 or CPU32+ core,
           including the 68330, 68331, 68332, 68333, 68334, 68336, 68340,
           68341, 68349 and 68360.

       -m5200
           Generate output for a 520X ColdFire CPU.  This is the default when
           the compiler is configured for 520X-based systems.  It is
           equivalent to -mcpu=5206, and is now deprecated in favor of that
           option.

           Use this option for microcontroller with a 5200 core, including the
           MCF5202, MCF5203, MCF5204 and MCF5206.

       -m5206e
           Generate output for a 5206e ColdFire CPU.  The option is now
           deprecated in favor of the equivalent -mcpu=5206e.

       -m528x
           Generate output for a member of the ColdFire 528X family.  The
           option is now deprecated in favor of the equivalent -mcpu=528x.

       -m5307
           Generate output for a ColdFire 5307 CPU.  The option is now
           deprecated in favor of the equivalent -mcpu=5307.

       -m5407
           Generate output for a ColdFire 5407 CPU.  The option is now
           deprecated in favor of the equivalent -mcpu=5407.

       -mcfv4e
           Generate output for a ColdFire V4e family CPU (e.g. 547x/548x).
           This includes use of hardware floating point instructions.  The
           option is equivalent to -mcpu=547x, and is now deprecated in favor
           of that option.

       -m68020-40
           Generate output for a 68040, without using any of the new
           instructions.  This results in code which can run relatively
           efficiently on either a 68020/68881 or a 68030 or a 68040.  The
           generated code does use the 68881 instructions that are emulated on
           the 68040.

           The option is equivalent to -march=68020 -mtune=68020-40.

       -m68020-60
           Generate output for a 68060, without using any of the new
           instructions.  This results in code which can run relatively
           efficiently on either a 68020/68881 or a 68030 or a 68040.  The
           generated code does use the 68881 instructions that are emulated on
           the 68060.

           The option is equivalent to -march=68020 -mtune=68020-60.

       -mhard-float
       -m68881
           Generate floating-point instructions.  This is the default for
           68020 and above, and for ColdFire devices that have an FPU.  It
           defines the macro __HAVE_68881__ on M680x0 targets and __mcffpu__
           on ColdFire targets.

       -msoft-float
           Do not generate floating-point instructions; use library calls
           instead.  This is the default for 68000, 68010, and 68832 targets.
           It is also the default for ColdFire devices that have no FPU.

       -mdiv
       -mno-div
           Generate (do not generate) ColdFire hardware divide and remainder
           instructions.  If -march is used without -mcpu, the default is "on"
           for ColdFire architectures and "off" for M680x0 architectures.
           Otherwise, the default is taken from the target CPU (either the
           default CPU, or the one specified by -mcpu).  For example, the
           default is "off" for -mcpu=5206 and "on" for -mcpu=5206e.

           gcc defines the macro __mcfhwdiv__ when this option is enabled.

       -mshort
           Consider type "int" to be 16 bits wide, like "short int".
           Additionally, parameters passed on the stack are also aligned to a
           16-bit boundary even on targets whose API mandates promotion to
           32-bit.

       -mno-short
           Do not consider type "int" to be 16 bits wide.  This is the
           default.

       -mnobitfield
       -mno-bitfield
           Do not use the bit-field instructions.  The -m68000, -mcpu32 and
           -m5200 options imply -mnobitfield.

       -mbitfield
           Do use the bit-field instructions.  The -m68020 option implies
           -mbitfield.  This is the default if you use a configuration
           designed for a 68020.

       -mrtd
           Use a different function-calling convention, in which functions
           that take a fixed number of arguments return with the "rtd"
           instruction, which pops their arguments while returning.  This
           saves one instruction in the caller since there is no need to pop
           the arguments there.

           This calling convention is incompatible with the one normally used
           on Unix, so you cannot use it if you need to call libraries
           compiled with the Unix compiler.

           Also, you must provide function prototypes for all functions that
           take variable numbers of arguments (including "printf"); otherwise
           incorrect code will be generated for calls to those functions.

           In addition, seriously incorrect code will result if you call a
           function with too many arguments.  (Normally, extra arguments are
           harmlessly ignored.)

           The "rtd" instruction is supported by the 68010, 68020, 68030,
           68040, 68060 and CPU32 processors, but not by the 68000 or 5200.

       -mno-rtd
           Do not use the calling conventions selected by -mrtd.  This is the
           default.

       -malign-int
       -mno-align-int
           Control whether GCC aligns "int", "long", "long long", "float",
           "double", and "long double" variables on a 32-bit boundary
           (-malign-int) or a 16-bit boundary (-mno-align-int).  Aligning
           variables on 32-bit boundaries produces code that runs somewhat
           faster on processors with 32-bit busses at the expense of more
           memory.

           Warning: if you use the -malign-int switch, GCC will align
           structures containing the above types  differently than most
           published application binary interface specifications for the m68k.

       -mpcrel
           Use the pc-relative addressing mode of the 68000 directly, instead
           of using a global offset table.  At present, this option implies
           -fpic, allowing at most a 16-bit offset for pc-relative addressing.
           -fPIC is not presently supported with -mpcrel, though this could be
           supported for 68020 and higher processors.

       -mno-strict-align
       -mstrict-align
           Do not (do) assume that unaligned memory references will be handled
           by the system.

       -msep-data
           Generate code that allows the data segment to be located in a
           different area of memory from the text segment.  This allows for
           execute in place in an environment without virtual memory
           management.  This option implies -fPIC.

       -mno-sep-data
           Generate code that assumes that the data segment follows the text
           segment.  This is the default.

       -mid-shared-library
           Generate code that supports shared libraries via the library ID
           method.  This allows for execute in place and shared libraries in
           an environment without virtual memory management.  This option
           implies -fPIC.

       -mno-id-shared-library
           Generate code that doesn't assume ID based shared libraries are
           being used.  This is the default.

       -mshared-library-id=n
           Specified the identification number of the ID based shared library
           being compiled.  Specifying a value of 0 will generate more compact
           code, specifying other values will force the allocation of that
           number to the current library but is no more space or time
           efficient than omitting this option.

       -mxgot
       -mno-xgot
           When generating position-independent code for ColdFire, generate
           code that works if the GOT has more than 8192 entries.  This code
           is larger and slower than code generated without this option.  On
           M680x0 processors, this option is not needed; -fPIC suffices.

           GCC normally uses a single instruction to load values from the GOT.
           While this is relatively efficient, it only works if the GOT is
           smaller than about 64k.  Anything larger causes the linker to
           report an error such as:

                   relocation truncated to fit: R_68K_GOT16O foobar

           If this happens, you should recompile your code with -mxgot.  It
           should then work with very large GOTs.  However, code generated
           with -mxgot is less efficient, since it takes 4 instructions to
           fetch the value of a global symbol.

           Note that some linkers, including newer versions of the GNU linker,
           can create multiple GOTs and sort GOT entries.  If you have such a
           linker, you should only need to use -mxgot when compiling a single
           object file that accesses more than 8192 GOT entries.  Very few do.

           These options have no effect unless GCC is generating position-
           independent code.

       M68hc1x Options

       These are the -m options defined for the 68hc11 and 68hc12
       microcontrollers.  The default values for these options depends on
       which style of microcontroller was selected when the compiler was
       configured; the defaults for the most common choices are given below.

       -m6811
       -m68hc11
           Generate output for a 68HC11.  This is the default when the
           compiler is configured for 68HC11-based systems.

       -m6812
       -m68hc12
           Generate output for a 68HC12.  This is the default when the
           compiler is configured for 68HC12-based systems.

       -m68S12
       -m68hcs12
           Generate output for a 68HCS12.

       -mauto-incdec
           Enable the use of 68HC12 pre and post auto-increment and auto-
           decrement addressing modes.

       -minmax
       -nominmax
           Enable the use of 68HC12 min and max instructions.

       -mlong-calls
       -mno-long-calls
           Treat all calls as being far away (near).  If calls are assumed to
           be far away, the compiler will use the "call" instruction to call a
           function and the "rtc" instruction for returning.

       -mshort
           Consider type "int" to be 16 bits wide, like "short int".

       -msoft-reg-count=count
           Specify the number of pseudo-soft registers which are used for the
           code generation.  The maximum number is 32.  Using more pseudo-soft
           register may or may not result in better code depending on the
           program.  The default is 4 for 68HC11 and 2 for 68HC12.

       MCore Options

       These are the -m options defined for the Motorola M*Core processors.

       -mhardlit
       -mno-hardlit
           Inline constants into the code stream if it can be done in two
           instructions or less.

       -mdiv
       -mno-div
           Use the divide instruction.  (Enabled by default).

       -mrelax-immediate
       -mno-relax-immediate
           Allow arbitrary sized immediates in bit operations.

       -mwide-bitfields
       -mno-wide-bitfields
           Always treat bit-fields as int-sized.

       -m4byte-functions
       -mno-4byte-functions
           Force all functions to be aligned to a four byte boundary.

       -mcallgraph-data
       -mno-callgraph-data
           Emit callgraph information.

       -mslow-bytes
       -mno-slow-bytes
           Prefer word access when reading byte quantities.

       -mlittle-endian
       -mbig-endian
           Generate code for a little endian target.

       -m210
       -m340
           Generate code for the 210 processor.

       -mno-lsim
           Assume that run-time support has been provided and so omit the
           simulator library (libsim.a) from the linker command line.

       -mstack-increment=size
           Set the maximum amount for a single stack increment operation.
           Large values can increase the speed of programs which contain
           functions that need a large amount of stack space, but they can
           also trigger a segmentation fault if the stack is extended too
           much.  The default value is 0x1000.

       MIPS Options

       -EB Generate big-endian code.

       -EL Generate little-endian code.  This is the default for mips*el-*-*
           configurations.

       -march=arch
           Generate code that will run on arch, which can be the name of a
           generic MIPS ISA, or the name of a particular processor.  The ISA
           names are: mips1, mips2, mips3, mips4, mips32, mips32r2, mips64 and
           mips64r2.  The processor names are: 4kc, 4km, 4kp, 4ksc, 4kec,
           4kem, 4kep, 4ksd, 5kc, 5kf, 20kc, 24kc, 24kf2_1, 24kf1_1, 24kec,
           24kef2_1, 24kef1_1, 34kc, 34kf2_1, 34kf1_1, 74kc, 74kf2_1, 74kf1_1,
           74kf3_2, loongson2e, loongson2f, m4k, octeon, orion, r2000, r3000,
           r3900, r4000, r4400, r4600, r4650, r6000, r8000, rm7000, rm9000,
           r10000, r12000, r14000, r16000, sb1, sr71000, vr4100, vr4111,
           vr4120, vr4130, vr4300, vr5000, vr5400, vr5500 and xlr.  The
           special value from-abi selects the most compatible architecture for
           the selected ABI (that is, mips1 for 32-bit ABIs and mips3 for
           64-bit ABIs).

           Native Linux/GNU toolchains also support the value native, which
           selects the best architecture option for the host processor.
           -march=native has no effect if GCC does not recognize the
           processor.

           In processor names, a final 000 can be abbreviated as k (for
           example, -march=r2k).  Prefixes are optional, and vr may be written
           r.

           Names of the form nf2_1 refer to processors with FPUs clocked at
           half the rate of the core, names of the form nf1_1 refer to
           processors with FPUs clocked at the same rate as the core, and
           names of the form nf3_2 refer to processors with FPUs clocked a
           ratio of 3:2 with respect to the core.  For compatibility reasons,
           nf is accepted as a synonym for nf2_1 while nx and bfx are accepted
           as synonyms for nf1_1.

           GCC defines two macros based on the value of this option.  The
           first is _MIPS_ARCH, which gives the name of target architecture,
           as a string.  The second has the form _MIPS_ARCH_foo, where foo is
           the capitalized value of _MIPS_ARCH.  For example, -march=r2000
           will set _MIPS_ARCH to "r2000" and define the macro
           _MIPS_ARCH_R2000.

           Note that the _MIPS_ARCH macro uses the processor names given
           above.  In other words, it will have the full prefix and will not
           abbreviate 000 as k.  In the case of from-abi, the macro names the
           resolved architecture (either "mips1" or "mips3").  It names the
           default architecture when no -march option is given.

       -mtune=arch
           Optimize for arch.  Among other things, this option controls the
           way instructions are scheduled, and the perceived cost of
           arithmetic operations.  The list of arch values is the same as for
           -march.

           When this option is not used, GCC will optimize for the processor
           specified by -march.  By using -march and -mtune together, it is
           possible to generate code that will run on a family of processors,
           but optimize the code for one particular member of that family.

           -mtune defines the macros _MIPS_TUNE and _MIPS_TUNE_foo, which work
           in the same way as the -march ones described above.

       -mips1
           Equivalent to -march=mips1.

       -mips2
           Equivalent to -march=mips2.

       -mips3
           Equivalent to -march=mips3.

       -mips4
           Equivalent to -march=mips4.

       -mips32
           Equivalent to -march=mips32.

       -mips32r2
           Equivalent to -march=mips32r2.

       -mips64
           Equivalent to -march=mips64.

       -mips64r2
           Equivalent to -march=mips64r2.

       -mips16
       -mno-mips16
           Generate (do not generate) MIPS16 code.  If GCC is targetting a
           MIPS32 or MIPS64 architecture, it will make use of the MIPS16e ASE.

           MIPS16 code generation can also be controlled on a per-function
           basis by means of "mips16" and "nomips16" attributes.

       -mflip-mips16
           Generate MIPS16 code on alternating functions.  This option is
           provided for regression testing of mixed MIPS16/non-MIPS16 code
           generation, and is not intended for ordinary use in compiling user
           code.

       -minterlink-mips16
       -mno-interlink-mips16
           Require (do not require) that non-MIPS16 code be link-compatible
           with MIPS16 code.

           For example, non-MIPS16 code cannot jump directly to MIPS16 code;
           it must either use a call or an indirect jump.  -minterlink-mips16
           therefore disables direct jumps unless GCC knows that the target of
           the jump is not MIPS16.

       -mabi=32
       -mabi=o64
       -mabi=n32
       -mabi=64
       -mabi=eabi
           Generate code for the given ABI.

           Note that the EABI has a 32-bit and a 64-bit variant.  GCC normally
           generates 64-bit code when you select a 64-bit architecture, but
           you can use -mgp32 to get 32-bit code instead.

           For information about the O64 ABI, see
           .

           GCC supports a variant of the o32 ABI in which floating-point
           registers are 64 rather than 32 bits wide.  You can select this
           combination with -mabi=32 -mfp64.  This ABI relies on the mthc1 and
           mfhc1 instructions and is therefore only supported for MIPS32R2
           processors.

           The register assignments for arguments and return values remain the
           same, but each scalar value is passed in a single 64-bit register
           rather than a pair of 32-bit registers.  For example, scalar
           floating-point values are returned in $f0 only, not a $f0/$f1 pair.
           The set of call-saved registers also remains the same, but all 64
           bits are saved.

       -mabicalls
       -mno-abicalls
           Generate (do not generate) code that is suitable for SVR4-style
           dynamic objects.  -mabicalls is the default for SVR4-based systems.

       -mshared
       -mno-shared
           Generate (do not generate) code that is fully position-independent,
           and that can therefore be linked into shared libraries.  This
           option only affects -mabicalls.

           All -mabicalls code has traditionally been position-independent,
           regardless of options like -fPIC and -fpic.  However, as an
           extension, the GNU toolchain allows executables to use absolute
           accesses for locally-binding symbols.  It can also use shorter GP
           initialization sequences and generate direct calls to locally-
           defined functions.  This mode is selected by -mno-shared.

           -mno-shared depends on binutils 2.16 or higher and generates
           objects that can only be linked by the GNU linker.  However, the
           option does not affect the ABI of the final executable; it only
           affects the ABI of relocatable objects.  Using -mno-shared will
           generally make executables both smaller and quicker.

           -mshared is the default.

       -mplt
       -mno-plt
           Assume (do not assume) that the static and dynamic linkers support
           PLTs and copy relocations.  This option only affects -mno-shared
           -mabicalls.  For the n64 ABI, this option has no effect without
           -msym32.

           You can make -mplt the default by configuring GCC with
           --with-mips-plt.  The default is -mno-plt otherwise.

       -mxgot
       -mno-xgot
           Lift (do not lift) the usual restrictions on the size of the global
           offset table.

           GCC normally uses a single instruction to load values from the GOT.
           While this is relatively efficient, it will only work if the GOT is
           smaller than about 64k.  Anything larger will cause the linker to
           report an error such as:

                   relocation truncated to fit: R_MIPS_GOT16 foobar

           If this happens, you should recompile your code with -mxgot.  It
           should then work with very large GOTs, although it will also be
           less efficient, since it will take three instructions to fetch the
           value of a global symbol.

           Note that some linkers can create multiple GOTs.  If you have such
           a linker, you should only need to use -mxgot when a single object
           file accesses more than 64k's worth of GOT entries.  Very few do.

           These options have no effect unless GCC is generating position
           independent code.

       -mgp32
           Assume that general-purpose registers are 32 bits wide.

       -mgp64
           Assume that general-purpose registers are 64 bits wide.

       -mfp32
           Assume that floating-point registers are 32 bits wide.

       -mfp64
           Assume that floating-point registers are 64 bits wide.

       -mhard-float
           Use floating-point coprocessor instructions.

       -msoft-float
           Do not use floating-point coprocessor instructions.  Implement
           floating-point calculations using library calls instead.

       -msingle-float
           Assume that the floating-point coprocessor only supports single-
           precision operations.

       -mdouble-float
           Assume that the floating-point coprocessor supports double-
           precision operations.  This is the default.

       -mllsc
       -mno-llsc
           Use (do not use) ll, sc, and sync instructions to implement atomic
           memory built-in functions.  When neither option is specified, GCC
           will use the instructions if the target architecture supports them.

           -mllsc is useful if the runtime environment can emulate the
           instructions and -mno-llsc can be useful when compiling for
           nonstandard ISAs.  You can make either option the default by
           configuring GCC with --with-llsc and --without-llsc respectively.
           --with-llsc is the default for some configurations; see the
           installation documentation for details.

       -mdsp
       -mno-dsp
           Use (do not use) revision 1 of the MIPS DSP ASE.
             This option defines the preprocessor macro __mips_dsp.  It also
           defines __mips_dsp_rev to 1.

       -mdspr2
       -mno-dspr2
           Use (do not use) revision 2 of the MIPS DSP ASE.
             This option defines the preprocessor macros __mips_dsp and
           __mips_dspr2.  It also defines __mips_dsp_rev to 2.

       -msmartmips
       -mno-smartmips
           Use (do not use) the MIPS SmartMIPS ASE.

       -mpaired-single
       -mno-paired-single
           Use (do not use) paired-single floating-point instructions.
             This option requires hardware floating-point support to be
           enabled.

       -mdmx
       -mno-mdmx
           Use (do not use) MIPS Digital Media Extension instructions.  This
           option can only be used when generating 64-bit code and requires
           hardware floating-point support to be enabled.

       -mips3d
       -mno-mips3d
           Use (do not use) the MIPS-3D ASE.  The option -mips3d implies
           -mpaired-single.

       -mmt
       -mno-mt
           Use (do not use) MT Multithreading instructions.

       -mlong64
           Force "long" types to be 64 bits wide.  See -mlong32 for an
           explanation of the default and the way that the pointer size is
           determined.

       -mlong32
           Force "long", "int", and pointer types to be 32 bits wide.

           The default size of "int"s, "long"s and pointers depends on the
           ABI.  All the supported ABIs use 32-bit "int"s.  The n64 ABI uses
           64-bit "long"s, as does the 64-bit EABI; the others use 32-bit
           "long"s.  Pointers are the same size as "long"s, or the same size
           as integer registers, whichever is smaller.

       -msym32
       -mno-sym32
           Assume (do not assume) that all symbols have 32-bit values,
           regardless of the selected ABI.  This option is useful in
           combination with -mabi=64 and -mno-abicalls because it allows GCC
           to generate shorter and faster references to symbolic addresses.

       -G num
           Put definitions of externally-visible data in a small data section
           if that data is no bigger than num bytes.  GCC can then access the
           data more efficiently; see -mgpopt for details.

           The default -G option depends on the configuration.

       -mlocal-sdata
       -mno-local-sdata
           Extend (do not extend) the -G behavior to local data too, such as
           to static variables in C.  -mlocal-sdata is the default for all
           configurations.

           If the linker complains that an application is using too much small
           data, you might want to try rebuilding the less performance-
           critical parts with -mno-local-sdata.  You might also want to build
           large libraries with -mno-local-sdata, so that the libraries leave
           more room for the main program.

       -mextern-sdata
       -mno-extern-sdata
           Assume (do not assume) that externally-defined data will be in a
           small data section if that data is within the -G limit.
           -mextern-sdata is the default for all configurations.

           If you compile a module Mod with -mextern-sdata -G num -mgpopt, and
           Mod references a variable Var that is no bigger than num bytes, you
           must make sure that Var is placed in a small data section.  If Var
           is defined by another module, you must either compile that module
           with a high-enough -G setting or attach a "section" attribute to
           Var's definition.  If Var is common, you must link the application
           with a high-enough -G setting.

           The easiest way of satisfying these restrictions is to compile and
           link every module with the same -G option.  However, you may wish
           to build a library that supports several different small data
           limits.  You can do this by compiling the library with the highest
           supported -G setting and additionally using -mno-extern-sdata to
           stop the library from making assumptions about externally-defined
           data.

       -mgpopt
       -mno-gpopt
           Use (do not use) GP-relative accesses for symbols that are known to
           be in a small data section; see -G, -mlocal-sdata and
           -mextern-sdata.  -mgpopt is the default for all configurations.

           -mno-gpopt is useful for cases where the $gp register might not
           hold the value of "_gp".  For example, if the code is part of a
           library that might be used in a boot monitor, programs that call
           boot monitor routines will pass an unknown value in $gp.  (In such
           situations, the boot monitor itself would usually be compiled with
           -G0.)

           -mno-gpopt implies -mno-local-sdata and -mno-extern-sdata.

       -membedded-data
       -mno-embedded-data
           Allocate variables to the read-only data section first if possible,
           then next in the small data section if possible, otherwise in data.
           This gives slightly slower code than the default, but reduces the
           amount of RAM required when executing, and thus may be preferred
           for some embedded systems.

       -muninit-const-in-rodata
       -mno-uninit-const-in-rodata
           Put uninitialized "const" variables in the read-only data section.
           This option is only meaningful in conjunction with -membedded-data.

       -mcode-readable=setting
           Specify whether GCC may generate code that reads from executable
           sections.  There are three possible settings:

           -mcode-readable=yes
               Instructions may freely access executable sections.  This is
               the default setting.

           -mcode-readable=pcrel
               MIPS16 PC-relative load instructions can access executable
               sections, but other instructions must not do so.  This option
               is useful on 4KSc and 4KSd processors when the code TLBs have
               the Read Inhibit bit set.  It is also useful on processors that
               can be configured to have a dual instruction/data SRAM
               interface and that, like the M4K, automatically redirect PC-
               relative loads to the instruction RAM.

           -mcode-readable=no
               Instructions must not access executable sections.  This option
               can be useful on targets that are configured to have a dual
               instruction/data SRAM interface but that (unlike the M4K) do
               not automatically redirect PC-relative loads to the instruction
               RAM.

       -msplit-addresses
       -mno-split-addresses
           Enable (disable) use of the "%hi()" and "%lo()" assembler
           relocation operators.  This option has been superseded by
           -mexplicit-relocs but is retained for backwards compatibility.

       -mexplicit-relocs
       -mno-explicit-relocs
           Use (do not use) assembler relocation operators when dealing with
           symbolic addresses.  The alternative, selected by
           -mno-explicit-relocs, is to use assembler macros instead.

           -mexplicit-relocs is the default if GCC was configured to use an
           assembler that supports relocation operators.

       -mcheck-zero-division
       -mno-check-zero-division
           Trap (do not trap) on integer division by zero.

           The default is -mcheck-zero-division.

       -mdivide-traps
       -mdivide-breaks
           MIPS systems check for division by zero by generating either a
           conditional trap or a break instruction.  Using traps results in
           smaller code, but is only supported on MIPS II and later.  Also,
           some versions of the Linux kernel have a bug that prevents trap
           from generating the proper signal ("SIGFPE").  Use -mdivide-traps
           to allow conditional traps on architectures that support them and
           -mdivide-breaks to force the use of breaks.

           The default is usually -mdivide-traps, but this can be overridden
           at configure time using --with-divide=breaks.  Divide-by-zero
           checks can be completely disabled using -mno-check-zero-division.

       -mmemcpy
       -mno-memcpy
           Force (do not force) the use of "memcpy()" for non-trivial block
           moves.  The default is -mno-memcpy, which allows GCC to inline most
           constant-sized copies.

       -mlong-calls
       -mno-long-calls
           Disable (do not disable) use of the "jal" instruction.  Calling
           functions using "jal" is more efficient but requires the caller and
           callee to be in the same 256 megabyte segment.

           This option has no effect on abicalls code.  The default is
           -mno-long-calls.

       -mmad
       -mno-mad
           Enable (disable) use of the "mad", "madu" and "mul" instructions,
           as provided by the R4650 ISA.

       -mfused-madd
       -mno-fused-madd
           Enable (disable) use of the floating point multiply-accumulate
           instructions, when they are available.  The default is
           -mfused-madd.

           When multiply-accumulate instructions are used, the intermediate
           product is calculated to infinite precision and is not subject to
           the FCSR Flush to Zero bit.  This may be undesirable in some
           circumstances.

       -nocpp
           Tell the MIPS assembler to not run its preprocessor over user
           assembler files (with a .s suffix) when assembling them.

       -mfix-r4000
       -mno-fix-r4000
           Work around certain R4000 CPU errata:

           -   A double-word or a variable shift may give an incorrect result
               if executed immediately after starting an integer division.

           -   A double-word or a variable shift may give an incorrect result
               if executed while an integer multiplication is in progress.

           -   An integer division may give an incorrect result if started in
               a delay slot of a taken branch or a jump.

       -mfix-r4400
       -mno-fix-r4400
           Work around certain R4400 CPU errata:

           -   A double-word or a variable shift may give an incorrect result
               if executed immediately after starting an integer division.

       -mfix-r10000
       -mno-fix-r10000
           Work around certain R10000 errata:

           -   "ll"/"sc" sequences may not behave atomically on revisions
               prior to 3.0.  They may deadlock on revisions 2.6 and earlier.

           This option can only be used if the target architecture supports
           branch-likely instructions.  -mfix-r10000 is the default when
           -march=r10000 is used; -mno-fix-r10000 is the default otherwise.

       -mfix-vr4120
       -mno-fix-vr4120
           Work around certain VR4120 errata:

           -   "dmultu" does not always produce the correct result.

           -   "div" and "ddiv" do not always produce the correct result if
               one of the operands is negative.

           The workarounds for the division errata rely on special functions
           in libgcc.a.  At present, these functions are only provided by the
           "mips64vr*-elf" configurations.

           Other VR4120 errata require a nop to be inserted between certain
           pairs of instructions.  These errata are handled by the assembler,
           not by GCC itself.

       -mfix-vr4130
           Work around the VR4130 "mflo"/"mfhi" errata.  The workarounds are
           implemented by the assembler rather than by GCC, although GCC will
           avoid using "mflo" and "mfhi" if the VR4130 "macc", "macchi",
           "dmacc" and "dmacchi" instructions are available instead.

       -mfix-sb1
       -mno-fix-sb1
           Work around certain SB-1 CPU core errata.  (This flag currently
           works around the SB-1 revision 2 "F1" and "F2" floating point
           errata.)

       -mr10k-cache-barrier=setting
           Specify whether GCC should insert cache barriers to avoid the side-
           effects of speculation on R10K processors.

           In common with many processors, the R10K tries to predict the
           outcome of a conditional branch and speculatively executes
           instructions from the "taken" branch.  It later aborts these
           instructions if the predicted outcome was wrong.  However, on the
           R10K, even aborted instructions can have side effects.

           This problem only affects kernel stores and, depending on the
           system, kernel loads.  As an example, a speculatively-executed
           store may load the target memory into cache and mark the cache line
           as dirty, even if the store itself is later aborted.  If a DMA
           operation writes to the same area of memory before the "dirty" line
           is flushed, the cached data will overwrite the DMA-ed data.  See
           the R10K processor manual for a full description, including other
           potential problems.

           One workaround is to insert cache barrier instructions before every
           memory access that might be speculatively executed and that might
           have side effects even if aborted.  -mr10k-cache-barrier=setting
           controls GCC's implementation of this workaround.  It assumes that
           aborted accesses to any byte in the following regions will not have
           side effects:

           1.  the memory occupied by the current function's stack frame;

           2.  the memory occupied by an incoming stack argument;

           3.  the memory occupied by an object with a link-time-constant
               address.

           It is the kernel's responsibility to ensure that speculative
           accesses to these regions are indeed safe.

           If the input program contains a function declaration such as:

                   void foo (void);

           then the implementation of "foo" must allow "j foo" and "jal foo"
           to be executed speculatively.  GCC honors this restriction for
           functions it compiles itself.  It expects non-GCC functions (such
           as hand-written assembly code) to do the same.

           The option has three forms:

           -mr10k-cache-barrier=load-store
               Insert a cache barrier before a load or store that might be
               speculatively executed and that might have side effects even if
               aborted.

           -mr10k-cache-barrier=store
               Insert a cache barrier before a store that might be
               speculatively executed and that might have side effects even if
               aborted.

           -mr10k-cache-barrier=none
               Disable the insertion of cache barriers.  This is the default
               setting.

       -mflush-func=func
       -mno-flush-func
           Specifies the function to call to flush the I and D caches, or to
           not call any such function.  If called, the function must take the
           same arguments as the common "_flush_func()", that is, the address
           of the memory range for which the cache is being flushed, the size
           of the memory range, and the number 3 (to flush both caches).  The
           default depends on the target GCC was configured for, but commonly
           is either _flush_func or __cpu_flush.

       mbranch-cost=num
           Set the cost of branches to roughly num "simple" instructions.
           This cost is only a heuristic and is not guaranteed to produce
           consistent results across releases.  A zero cost redundantly
           selects the default, which is based on the -mtune setting.

       -mbranch-likely
       -mno-branch-likely
           Enable or disable use of Branch Likely instructions, regardless of
           the default for the selected architecture.  By default, Branch
           Likely instructions may be generated if they are supported by the
           selected architecture.  An exception is for the MIPS32 and MIPS64
           architectures and processors which implement those architectures;
           for those, Branch Likely instructions will not be generated by
           default because the MIPS32 and MIPS64 architectures specifically
           deprecate their use.

       -mfp-exceptions
       -mno-fp-exceptions
           Specifies whether FP exceptions are enabled.  This affects how we
           schedule FP instructions for some processors.  The default is that
           FP exceptions are enabled.

           For instance, on the SB-1, if FP exceptions are disabled, and we
           are emitting 64-bit code, then we can use both FP pipes.
           Otherwise, we can only use one FP pipe.

       -mvr4130-align
       -mno-vr4130-align
           The VR4130 pipeline is two-way superscalar, but can only issue two
           instructions together if the first one is 8-byte aligned.  When
           this option is enabled, GCC will align pairs of instructions that
           it thinks should execute in parallel.

           This option only has an effect when optimizing for the VR4130.  It
           normally makes code faster, but at the expense of making it bigger.
           It is enabled by default at optimization level -O3.

       MMIX Options

       These options are defined for the MMIX:

       -mlibfuncs
       -mno-libfuncs
           Specify that intrinsic library functions are being compiled,
           passing all values in registers, no matter the size.

       -mepsilon
       -mno-epsilon
           Generate floating-point comparison instructions that compare with
           respect to the "rE" epsilon register.

       -mabi=mmixware
       -mabi=gnu
           Generate code that passes function parameters and return values
           that (in the called function) are seen as registers $0 and up, as
           opposed to the GNU ABI which uses global registers $231 and up.

       -mzero-extend
       -mno-zero-extend
           When reading data from memory in sizes shorter than 64 bits, use
           (do not use) zero-extending load instructions by default, rather
           than sign-extending ones.

       -mknuthdiv
       -mno-knuthdiv
           Make the result of a division yielding a remainder have the same
           sign as the divisor.  With the default, -mno-knuthdiv, the sign of
           the remainder follows the sign of the dividend.  Both methods are
           arithmetically valid, the latter being almost exclusively used.

       -mtoplevel-symbols
       -mno-toplevel-symbols
           Prepend (do not prepend) a : to all global symbols, so the assembly
           code can be used with the "PREFIX" assembly directive.

       -melf
           Generate an executable in the ELF format, rather than the default
           mmo format used by the mmix simulator.

       -mbranch-predict
       -mno-branch-predict
           Use (do not use) the probable-branch instructions, when static
           branch prediction indicates a probable branch.

       -mbase-addresses
       -mno-base-addresses
           Generate (do not generate) code that uses base addresses.  Using a
           base address automatically generates a request (handled by the
           assembler and the linker) for a constant to be set up in a global
           register.  The register is used for one or more base address
           requests within the range 0 to 255 from the value held in the
           register.  The generally leads to short and fast code, but the
           number of different data items that can be addressed is limited.
           This means that a program that uses lots of static data may require
           -mno-base-addresses.

       -msingle-exit
       -mno-single-exit
           Force (do not force) generated code to have a single exit point in
           each function.

       MN10300 Options

       These -m options are defined for Matsushita MN10300 architectures:

       -mmult-bug
           Generate code to avoid bugs in the multiply instructions for the
           MN10300 processors.  This is the default.

       -mno-mult-bug
           Do not generate code to avoid bugs in the multiply instructions for
           the MN10300 processors.

       -mam33
           Generate code which uses features specific to the AM33 processor.

       -mno-am33
           Do not generate code which uses features specific to the AM33
           processor.  This is the default.

       -mreturn-pointer-on-d0
           When generating a function which returns a pointer, return the
           pointer in both "a0" and "d0".  Otherwise, the pointer is returned
           only in a0, and attempts to call such functions without a prototype
           would result in errors.  Note that this option is on by default;
           use -mno-return-pointer-on-d0 to disable it.

       -mno-crt0
           Do not link in the C run-time initialization object file.

       -mrelax
           Indicate to the linker that it should perform a relaxation
           optimization pass to shorten branches, calls and absolute memory
           addresses.  This option only has an effect when used on the command
           line for the final link step.

           This option makes symbolic debugging impossible.

       PDP-11 Options

       These options are defined for the PDP-11:

       -mfpu
           Use hardware FPP floating point.  This is the default.  (FIS
           floating point on the PDP-11/40 is not supported.)

       -msoft-float
           Do not use hardware floating point.

       -mac0
           Return floating-point results in ac0 (fr0 in Unix assembler
           syntax).

       -mno-ac0
           Return floating-point results in memory.  This is the default.

       -m40
           Generate code for a PDP-11/40.

       -m45
           Generate code for a PDP-11/45.  This is the default.

       -m10
           Generate code for a PDP-11/10.

       -mbcopy-builtin
           Use inline "movmemhi" patterns for copying memory.  This is the
           default.

       -mbcopy
           Do not use inline "movmemhi" patterns for copying memory.

       -mint16
       -mno-int32
           Use 16-bit "int".  This is the default.

       -mint32
       -mno-int16
           Use 32-bit "int".

       -mfloat64
       -mno-float32
           Use 64-bit "float".  This is the default.

       -mfloat32
       -mno-float64
           Use 32-bit "float".

       -mabshi
           Use "abshi2" pattern.  This is the default.

       -mno-abshi
           Do not use "abshi2" pattern.

       -mbranch-expensive
           Pretend that branches are expensive.  This is for experimenting
           with code generation only.

       -mbranch-cheap
           Do not pretend that branches are expensive.  This is the default.

       -msplit
           Generate code for a system with split I&D.

       -mno-split
           Generate code for a system without split I&D.  This is the default.

       -munix-asm
           Use Unix assembler syntax.  This is the default when configured for
           pdp11-*-bsd.

       -mdec-asm
           Use DEC assembler syntax.  This is the default when configured for
           any PDP-11 target other than pdp11-*-bsd.

       picoChip Options

       These -m options are defined for picoChip implementations:

       -mae=ae_type
           Set the instruction set, register set, and instruction scheduling
           parameters for array element type ae_type.  Supported values for
           ae_type are ANY, MUL, and MAC.

           -mae=ANY selects a completely generic AE type.  Code generated with
           this option will run on any of the other AE types.  The code will
           not be as efficient as it would be if compiled for a specific AE
           type, and some types of operation (e.g., multiplication) will not
           work properly on all types of AE.

           -mae=MUL selects a MUL AE type.  This is the most useful AE type
           for compiled code, and is the default.

           -mae=MAC selects a DSP-style MAC AE.  Code compiled with this
           option may suffer from poor performance of byte (char)
           manipulation, since the DSP AE does not provide hardware support
           for byte load/stores.

       -msymbol-as-address
           Enable the compiler to directly use a symbol name as an address in
           a load/store instruction, without first loading it into a register.
           Typically, the use of this option will generate larger programs,
           which run faster than when the option isn't used.  However, the
           results vary from program to program, so it is left as a user
           option, rather than being permanently enabled.

       -mno-inefficient-warnings
           Disables warnings about the generation of inefficient code.  These
           warnings can be generated, for example, when compiling code which
           performs byte-level memory operations on the MAC AE type.  The MAC
           AE has no hardware support for byte-level memory operations, so all
           byte load/stores must be synthesized from word load/store
           operations.  This is inefficient and a warning will be generated
           indicating to the programmer that they should rewrite the code to
           avoid byte operations, or to target an AE type which has the
           necessary hardware support.  This option enables the warning to be
           turned off.